This invention relates to a method of producing a multi-level dual-gate ROM type memory in a CMOS process, and to a memory cell structure produced thereby.
The invention also relates to a ROM structure, with transistor cells integrated in a semiconductor by a dual gate CMOS process along with electrically erasable non-volatile memory cells and low- and high-voltage transistors, with all the cells and transistors having active areas covered with a layer of gate oxide, in turn overlaid by a polysilicon layer.
As is well known in this specific technical field, there exists a growing demand from the market, and especially from the smart card market, for integration in a single semiconductor electronic device of both ROM (Read Only Memory) circuits and non-volatile, but electrically erasable, memories such as EEPROMs and/or Flash EEPROMS. Filling this demand calls for a significantly more complicated manufacturing process than a process used to create only a single one of these memories, as the technologies involved in providing either circuit types are not fully compatible. Accordingly, production costs become higher, and achieving high yield rates is made more difficult. In addition, continuing advances in cryptographic techniques require the use of codes of increasing size, in terms of number of bits, which are not easily decrypted by reverse engineering methods.
It is also recognized that an array of ROM cells is essentially an array of MOS transistors having conventional source, drain, and gate terminals, and threshold voltages which are set during their fabrication process. The threshold is also differentiated such that, for any given bias of the transistor gate terminal, it becomes possible to determine which cells are in the xe2x80x98onxe2x80x99 (logic 1) state and which are instead in the xe2x80x98offxe2x80x99 (logic 0) state by means of a suitable sensing circuit. Telling which cells are in the logic 1 state and which are in the logic 0 state is usually achieved by implanting or not implanting the source and drain junctions during the step of implanting these transistor regions.
This prior approach provides cells with a logic value of 1 and/or 0, without a preliminary optical analysis enabling them to be discerned. Other approaches allow the logic value of 1 or 0 to be determined based on the presence or absence of a transistor.
There is no current technology available which can provide a multi-level ROM structure, that is, a structure which can store several logic values in each memory cell.
A method of producing a multi-level type of ROM in a CMOS process of the dual-gate type is presented, thereby expanding the information storage capacity by means of a readily integratable component with CMOS technology.
Embodiments of this invention provide a ROM type of memory cell which can store at least three discrete logic levels. Such a cell is obtained by two different dopings of the polysilicon layer that forms the gate region of the transistor. The step of implanting the source/drain regions of the transistor which comprises the cell is, therefore, substantially separated from the polysilicon implanting step.
Based on this concept, a memory device and a method of producing the multi-level memory of the ROM type in a CMOS process of the dual gate type is presented. First, on a semiconductor substrate, active areas for transistors including ROM cells, electrically erasable non-volatile memory cells, and low- and high- voltage transistors are created. Oxide and polysilicon layers are deposited over the semiconductor. The polysilicon layer is masked and etched to define respective gate regions of the ROM cells, non-volatile cells, and low- and high-voltage transistors. The polysilicon layer of some of the transistors of the ROM cells is masked and the substrate implanted by a dopant in the active areas of the exposed transistors. The mask is then removed, and a second dopant species is implanted in the semiconductor in areas previously covered by the mask. Finally, the polysilicon layer is masked and subsequently etched to define the gate regions of the ROM cell transistors.